The present invention relates to a computer which includes a plurality of operation units and which can execute a plurality of instructions in parallel.
A serial computer which serially executes one sequence of programs is typically formed of an instruction control unit and an operation unit. For the purpose of providing a computer which executes programs at a higher speed, it has been proposed to assemble a plurality of sets of the aforementioned units. However, such a computer does not properly operate in response to instruction sequence of the type indicated below:
Load--Register R1, R2 (R1.rarw.R2) PA0 Add--Register R3, R1 (R3.rarw.R5+R1) PA0 Subtract--Register R3, R0 (R3.rarw.R3-R0)
where R0, R1, R2 and R3 denote registers R0, R1, R2 and R3, respectively.
When a group of instructions whose executions are mutually interdependent are executed independently in parallel by a plurality of operation units, the final result (in this example, the content of R3) is not guaranteed. The reason is that the three instructions are executed quite independently, so that the operation result of a preceding instruction is not taken into consideration in the execution of a succeeding instruction. Such a condition is called an "operand conflict". In a prior-art computer, there is a single instruction control unit which performs the centralized control over operand conflicts in serial fashion, and the correct result is guaranteed even for an instruction sequence of the type mentioned above. More specifically, the start of the execution of the second instruction Add--Register is delayed until the executed result of the first instruction Load--Register has been obtained. The start of the execution of the third instruction Subtract--Register is delayed until the second instruction has read out the content of the R3 register and has written the executed result into the R3 register again. Also, in a prior-art computer which includes a plurality of pipeline operation units capable of operating simultaneously, there is only one instruction control unit, and only the decoding of a single instruction and the start of the operation unit corresponding to the single instruction are possible within one machine cycle. That is, the other operation units are idle during the cycle.